1. A method of manufacturing an integrated circuit (IC) package comprising:providing a printed circuit board and a first semiconductor die mounted on the printed circuit board, wherein the first semiconductor die comprises a first Back-End-of-Line (BEOL) region, a first Front-End-of-Line (FEOL) region, and a first semiconductor handle such that the first BEOL region, the first FEOL region, and the first semiconductor handle are stacked;
providing a first polymer layer over the printed circuit board so that the first polymer layer covers the first semiconductor die;
exposing an area of the first semiconductor handle through the first polymer layer; and
after exposing the area of the first semiconductor handle through the first polymer layer, removing the first semiconductor handle to provide a first void in the first polymer layer over the first BEOL region and the first FEOL region; and
providing a second polymer layer at least within the first void so that the first BEOL region, the first FEOL region, and at least a portion of the second polymer layer within the first void are stacked.