US Patent No. 9,935,069

REDUCING SOLDER PAD TOPOLOGY DIFFERENCES BY PLANARIZATION


Patent No. 9,935,069
Issue Date April 03, 2018
Title Reducing Solder Pad Topology Differences By Planarization
Inventorship Jipu Lei, San Jose, CA (US)
Stefano Schiaffino, San Jose, CA (US)
Alexander H. Nickel, San Jose, CA (US)
Mooi Guan Ng, San Jose, CA (US)
Salman Akram, San Jose, CA (US)
Assignee LUMILEDS LLC, San Jose, CA (US)

Claim of US Patent No. 9,935,069

1. A method comprising:providing an electronic device with a first surface and a second surface opposite the first surface;
providing a first solder pad at a first distance above the first surface and a second solder pad at second distance above the first surface, the first distance being different from the second distance;
providing a dielectric layer between the first solder pad and the second solder pad;
after the step of providing the dielectric layer, plating a first metal layer portion over the first solder pad above a height of the dielectric layer so that, immediately after the step of plating, the first metal layer portion extends above any insulating material;
after the step of providing the dielectric layer, plating a second metal layer portion, concurrently with plating the first metal layer portion, over the second solder pad above the height of the dielectric layer so that, immediately after the step of plating, the second metal layer portion extends above any insulating material;
planarizing the first metal layer portion and the second metal layer portion, so that the step of planarizing planarizes only the material forming the first metal layer portion and the second metal layer portion, resulting in the first metal layer and the second metal layer having a third and a fourth surface respectively, wherein the third surface and the fourth surface are in the same plane and still have a height above the height of the dielectric layer,
depositing a first solder layer over the first metal layer portion; and
depositing a second solder layer over the second metal layer portion, such that a top surface of the first solder layer is in the same plane as a top surface of the second solder layer.