1. An apparatus, comprising:an embedded system comprising:
a processor configured to execute firmware;
a random access memory (RAM) configured to store firmware and a multi-port memory controller configured to interface with the RAM;
a power-on reset (POR) sequencer configured to control a boot process of the embedded system, wherein the POR sequence controls the boot process and verifies an integrity of loaded data and code in the RAM;
a nonvolatile memory configured to store data used by the POR sequencer in the boot process and a nonvolatile memory controller configured to interface with the nonvolatile memory;
a direct memory access (DMA) controller configured initiate and track data transfers; and
a configuration and status register (CSR) controller configured to provide an interface for the processor to access configuration and status registers of the nonvolatile memory controller, a processor bus, a CSR bus, the DMA controller, and the multi-port memory controller in the embedded system;
wherein the embedded system verifies an integrity of data and code used in the boot process and wherein the embedded system reduces an amount of the nonvolatile memory used in the boot process to provide an advantage in terms of cost and complexity.