US Patent No. 9,832,883

INTEGRATED CIRCUIT PACKAGE SUBSTRATE


Patent No. 9,832,883
Issue Date November 28, 2017
Title Integrated Circuit Package Substrate
Inventorship Qinglei Zhang, Chandler, AZ (US)
Assignee Intel Corporation, Santa Clara, CA (US)

Claim of US Patent No. 9,832,883

1. A package substrate comprising:
a first side that includes one or more lands, the one or more lands with a first surface finish disposed on the one or more
lands;

a second side disposed opposite to the first side, the second side with an outer dielectric layer that has an outer surface,
the outer surface being an outer surface of the package substrate; and

one or more electrical routing features disposed in, and extending through, the outer dielectric layer, wherein the one or
more electrical routing features have an outer surface that is coplanar with the outer surface of the outer dielectric layer,
wherein a second surface finish is disposed on, and in direct contact with, the outer surface of the one or more electrical
routing features, wherein the one or more electrical routing features have a pitch to bond with die interconnect structures
of one or more dies, wherein the second surface finish has a different chemical composition than the first surface finish,
wherein a bump pitch of the electrical routing features is 50 micrometers, and wherein the electrical routing features include
a pad size of 49 micrometers.