US Patent No. 9,781,844

SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST


Patent No. 9,781,844
Issue Date October 03, 2017
Title Simultaneous And Selective Wide Gap Partitioning Of Via Structures Using Plating Resist
Inventorship Shinichi Iketani, San Jose, CA (US)
Dale Kersten, San Jose, CA (US)
Assignee SANMINA CORPORATION, San Jose, CA (US)

Claim of US Patent No. 9,781,844

1. A multilayer printed circuit board, comprising:
a first core or sub-composite structure;
a first plating resist selectively positioned on a first surface of the first core or sub-composite structure;
a second plating resist selectively positioned on a second surface of the first core or sub-composite structure or within
a dielectric layer of the first core or sub-composite structure, the second surface opposite the first surface;

one or more dielectric layers on each side of the first core or sub-composite structure; and
a through hole extending through the first core or sub-composite structure, the first plating resist, the second plating resist,
and the one or more dielectric layers, where an interior surface of the through hole is plated with a conductive material
except along a length between the first plating resist and the second plating resist to form a first internal via segment
electrically isolated from a second internal via segment along the plated through hole.