US Patent No. 9,781,830

SIMULTANEOUS AND SELECTIVE WIDE GAP PARTITIONING OF VIA STRUCTURES USING PLATING RESIST


Patent No. 9,781,830
Issue Date October 03, 2017
Title Simultaneous And Selective Wide Gap Partitioning Of Via Structures Using Plating Resist
Inventorship Shinichi Iketani, San Jose, CA (US)
Dale Kersten, San Jose, CA (US)
George Dudnikov, Jr., San Jose, CA (US)
Assignee Sanmina Corporation, San Jose, CA (US)

Claim of US Patent No. 9,781,830

1. A multilayer printed circuit board, comprising:
a first dielectric layer;
a first plating resist selectively positioned in the first dielectric layer;
a second plating resist selectively positioned in the first dielectric layer or a second dielectric layer, the second plating
resist separate from the first plating resist; and

a through hole extending through the first dielectric layer, the first plating resist, and the second plating resist, where
an interior surface of the through hole is plated with a conductive material except along a length between the first plating
resist and the second plating resist to form a partitioned plated through hole having a first via segment electrically isolated
from a second via segment.