US Patent No. 9,715,428

SYSTEM AND METHOD FOR CACHE DATA RECOVERY


Patent No. 9,715,428
Issue Date July 25, 2017
Title System And Method For Cache Data Recovery
Inventorship Abbas Morshed, Los Altos, CA (US)
Chuan-Wen George Tsang, San Jose, CA (US)
Christopher Youngworth, San Jose, CA (US)
Assignee Sanmina Corporation, San Joe, CA (US)

Claim of US Patent No. 9,715,428

1. A system comprising:
a first host device that includes a first host data buffer and a second host device that includes a second host data buffer;
first and second cache controllers, wherein each of the first cache controller and the second cache controller include:
a cache memory interface;
a first peripheral interface configured for communication with the first host device and a second peripheral interface configured
for communication with the second host device;

a first-in-first-out memory buffer (FIFO) configured to store cache commands loaded from at least one of the first and second
host devices; and

logic circuitry configured to load one or more cache commands over at least one of the first peripheral interface from a cache
command memory of the first host device to the FIFO and the second peripheral interface from a cache command memory of the
second host device to the FIFO, and to perform the cache commands, and to provide to a completion status signal to both the
first and second host devices in response to at least one of the cache commands;

wherein the first host device is configured to free data in the first host data buffer in response to receiving matching completion
status signals from both the first and second cache controllers in response to the at least one of the cache commands;

wherein the second host device is configured to free data in the second host data buffer in response to receiving matching
completion status signals from both the first and second cache controllers in response to the at least one of the cache commands;
and

wherein at least one of the first host device and the second host device is configured to write contents of at least one of
the cache memory of the second cache controller/memory pair and the cache memory of the first cache controller/memory pair
to a main memory in response to at least one of receiving nonmatching completion status signals from the first and second
cache controllers in response to the at least one of the cache commands and receiving no completion signal from at least one
of the first and second cache controllers.