US Patent No. 9,690,498

PROTECTED MODE FOR SECURING COMPUTING DEVICES


Patent No. 9,690,498
Issue Date June 27, 2017
Title Protected Mode For Securing Computing Devices
Inventorship Jerry Hutchison, Huntington Valley, PA (US)
Robert Coia, Lower Gwynedd, PA (US)
Assignee L3 TECHNOLOGIES, INC., New York, NY (US)

Claim of US Patent No. 9,690,498

1. A method for validating volatile memory, the method comprising:
determining a plurality of challenge parameters, wherein the plurality of challenge parameters are associated with a challenge
that is intended to bring volatile memory to a known state for validation, and the plurality of challenge parameters comprise
an indication of a memory region and a random number;

writing a pattern to at least one portion of unused volatile memory of the volatile memory, wherein writing the pattern to
the at least one portion of unused volatile memory comprises:

initializing a counter,
selecting at least one memory address on which the pattern is written based on a result of a pseudorandom function that takes
a current value of the counter as an input,

determining a value to write at the at least one memory address based on a value that was stored at another memory address
in the volatile memory and the current value of the counter that was used as the input to the pseudorandom function, and

writing the value at the at least one memory address;
determining that the volatile memory is ready for validation in accordance with the challenge; and
performing a validation procedure on the volatile memory.