US Patent No. 9,553,082

PROCESS FOR IMPROVING CRITICAL DIMENSION UNIFORMITY OF INTEGRATED CIRCUIT ARRAYS


Patent No. 9,553,082
Issue Date January 24, 2017
Title Process For Improving Critical Dimension Uniformity Of Integrated Circuit Arrays
Inventorship David Kewley, Boise, ID (US)
Assignee Micron Technology, Inc., Boise, ID (US)

Claim of US Patent No. 9,553,082

1. An intermediate structure of an integrated circuit, comprising:
a substrate comprising a target layer on the substrate and a hard mask layer on the substrate over the target layer, the substrate
comprising a repeating pattern of lines and spaces there-between on the substrate over the hard mask layer; and

a mask on the substrate over the repeating pattern of lines and spaces there-between and over the hard mask layer, the mask
comprising a plurality of spaced-apart array regions having a peripheral region between immediately laterally-adjacent of
the spaced-apart array

regions, the repeating pattern of the lines and the spaces there-between spanning across the immediately laterally-adjacent
spaced-apart array regions and across the peripheral region that is between the immediately laterally-adjacent spaced-apart
array regions.