US Patent No. 9,477,257

METHODS AND APPARATUS FOR LIMITING A NUMBER OF CURRENT CHANGES WHILE CLOCK GATING TO MANAGE POWER CONSUMPTION OF PROCESSOR MODULES


Patent No. 9,477,257
Issue Date October 25, 2016
Title Methods And Apparatus For Limiting A Number Of Current Changes While Clock Gating To Manage Power Consumption Of Processor Modules
Inventorship Vaishali Kulkarni, San Jose, CA (US)
Jeffrey G. Libby, Cupertino, CA (US)
Mihir Wagh, Mountain View, CA (US)
Assignee JUNIPER NETWORKS, INC., Sunnyvale, CA (US)

Claim of US Patent No. 9,477,257

1. An apparatus, comprising:
a dispatch module implemented in at least one of a memory or a processing device, the dispatch module configured to be operatively
coupled to a plurality of processing modules each having a first clock configuration and a second clock configuration,

the dispatch module configured to change, at a first time during a predetermined time period, a processing module from the
plurality of processing modules from the first clock configuration to the second clock configuration,

the dispatch module configured to prohibit a change in clock configuration of each processing module from the plurality of
processing modules from the first clock configuration to the second clock configuration at a second time after the first time
and within the predetermined time period if an indicator associated with a number of clock configuration changes between a
first clock configuration and a second clock configuration within the predetermined time period satisfies a criterion, the
criterion being based on a threshold number of times an electric current changes, within the predetermined time period, for
at least one of a chip package associated with the dispatch module or a power supply associated with the dispatch module.