US Patent No. 9,467,161

LOW-POWER, HIGH-SPEED SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND CONVERSION METHOD USING THE SAME


Patent No. 9,467,161
Issue Date October 11, 2016
Title Low-power, High-speed Successive Approximation Register Analog-to-digital Converter And Conversion Method Using The Same
Inventorship Chul Woo Kim, Seoul (KR)
Se Jin Park, Seoul (KR)
Assignee Korea University Research and Business Foundation, Seoul (KR)

Claim of US Patent No. 9,467,161

1. A low-power, high-speed successive approximation register (SAR) analog-to-digital converter (ADC) comprising:
a bootstrapping unit configured to receive inputs of first and second analog signals;
a double-bit output SAR analog-to-digital conversion unit configured to output a two-bit digital signal for each clock cycle
section with respect to the first and second analog signals applied through the bootstrapping unit; and

a single-bit output SAR analog-to-digital conversion unit configured to output a one-bit digital signal for each clock cycle
section with respect to the first and second analog signals applied through the bootstrapping unit;

wherein the bootstrapping unit includes first to third bootstrapping switch pairs,
wherein the first and second bootstrapping switch pairs apply the first and second analog signals to the double-bit output
SAR analog-to-digital conversion unit, and

wherein the third bootstrapping switch pair applies the first and second analog signals to the single-bit output SAR analog-to-digital
conversion unit.