US Patent No. 9,395,748

METHOD AND SYSTEM FOR TIME SYNCHRONIZATION IN A NETWORK DEVICE


Patent No. 9,395,748
Issue Date July 19, 2016
Title Method And System For Time Synchronization In A Network Device
Inventorship Deepak Sebastian, San Francisco, CA (US)
Assignee Arista Networks, Inc., Santa Clara, CA (US)

Claim of US Patent No. 9,395,748

8. A network device, the network device comprising:
a first system control device (SCD);
a second SCD;
a phase locked loop (PLL);
a line card system control device (LC-SCD);
a plurality of network chips; and
a plurality of ports,
wherein the first SCD sends a first clock signal to the PLL chip;
wherein the first SCD sends a first time of day (TOD) to the LC-SCD on a line card;
wherein the second SCD sends a second clock signal to the PLL chip;
wherein the second SCD sends a second TOD to the LC-SCD;
wherein the PLL chip generates a third clock signal and synchronizes the third clock signal to the first clock signal, wherein
the first system control device is operational;

wherein the PLL chip sends the third clock signal to at least one network chip of the plurality of network chips;
wherein the at least one network chip derives, using the third clock signal, a first network-chip-internal clock signal; and
wherein applies the first network-chip-internal clock signal to increment a network-chip-internal TOD to obtain a third TOD;
wherein the LC-SCD sends the first TOD to the at least one network chip;
wherein the at least one network chip calculates a first difference between the third TOD and the first TOD; and
wherein the at least one network chip applies the first difference to the third TOD in order to synchronize the third TOD
to the first TOD.