US Patent No. 9,391,045

RECESSED SEMICONDUCTOR SUBSTRATES AND ASSOCIATED TECHNIQUES


Patent No. 9,391,045
Issue Date July 12, 2016
Title Recessed Semiconductor Substrates And Associated Techniques
Inventorship Albert Wu, Palo Alto, CA (US)
Roawen Chen, San Jose, CA (US)
Chung Chyung (Justin) Han, San Jose, CA (US)
Shiann-Ming Liou, Campbell, CA (US)
Chien-Chuan Wei, San Diego, CA (US)
Runzi Chang, San Jose, CA (US)
Scott Wu, San Jose, CA (US)
Chuan-Cheng Cheng, Fremont, CA (US)
Assignee Marvell World Trade Ltd., St. Michael (BB)

Claim of US Patent No. 9,391,045

1. An apparatus comprising:
a semiconductor substrate having (i) a first surface, and (ii) a second surface that is opposite to the first surface;
a first redistribution layer deposited on the first surface of the semiconductor substrate;
a second redistribution layer deposited on the second surface of the semiconductor substrate;
a first die having (i) an active side and (ii) an inactive side that is disposed opposite to the active side of the first
die, wherein the active side of the first die is coupled to the first redistribution layer deposited on the first surface
of the semiconductor substrate;

a second die having (i) an active side and (ii) an inactive side that is disposed opposite to the active side of the second
die, wherein the active side of the second die is coupled to the second redistribution layer deposited on the second surface
of the semiconductor substrate;

a first package interconnect structure that is (i) deposited on the first surface of the semiconductor substrate and (ii)
in contact with a first external device, wherein the first package interconnect structure is configured to couple the first
redistribution layer to the first external device, and wherein the inactive side of the first die is physically attached to
the first external device; and

a second package interconnect structure deposited on the second surface of the semiconductor substrate, wherein the second
package interconnect structure is configured to couple the second redistribution layer to a second external device.