US Patent No. 9,379,621

DIGITAL SLOPE COMPENSATION FOR PEAK CURRENT CONTROLLED CONVERTERS


Patent No. 9,379,621
Issue Date June 28, 2016
Title Digital Slope Compensation For Peak Current Controlled Converters
Inventorship Sabarish Kalyanaranman, Bangalore (IN)
Ramesh Kankanala, Bangalore (IN)
Assignee MICROCHIP TECHNOLOGY INCORPORATED, Chandler, AZ (US)

Claim of US Patent No. 9,379,621

1. A method for providing slope compensation in a switched-mode power supply (SMPS) controller, said method comprising the
steps of:
turning on a pulse width modulation (PWM) control signal at a beginning of a PWM cycle;
sampling an input voltage (vin) to a SMPS;

converting the sampled input voltage (vin) to a digital representation thereof (VIN_D);

sampling an output voltage (vo) from the SMPS;

converting the sampled output voltage (vo) to a digital representation thereof (VOUT_D);

sampling an inductor current (IL) of the SMPS when the PWM control signal turns on at the beginning of the PWM cycle, wherein the inductor current (IL) is at a minimum inductor current value (IV);

converting the sampled minimum inductor current value (IV) to a digital representation thereof (IV_D);

determining a digital slope compensated peak current reference (ICMP_D) with a digital processor according to the steps of:

determining A, where A is a function of the digital representations of the sampled output voltage (VOUT_D) and the sampled input voltage (VIN_D),

for a buck converter topology

for a boost converter topology

for a buck-boost converter topology

wherein ? is within a range of 0.5 determining B, where B is a function of the digital representations of the sampled output voltage (VOUT_D) and the sampled input voltage (VIN_D),

for the buck converter topology

for the boost converter topology

for the buck-boost converter topology

wherein ? is within the range of 0.5 multiplying A of any of the buck converter topology, the boost converter topology and the buck-boost converter topology with
the digital minimum inductor current (IV_D),

multiplying B of any of the buck converter topology, the boost converter topology and the buck-boost converter topology with
a digital control reference current (IC_D), and

adding results of the multiplying A and the multiplying B to determine the digital slope compensated peak current reference
(ICMP_D=A*IV_D+B*IC_D);

converting the digital slope compensated peak current reference (ICMP_D) to an analog slope compensated peak current reference (ICMP) with a digital-to-analog converter (DAC);

comparing the analog slope compensated peak current reference (ICMP) to the inductor current (IL) with an analog comparator;

turning off the PWM control signal with an output from the analog comparator when the inductor current (IL) is substantially equal to the analog slope compensated peak current reference (ICMP); and

returning to the step of turning on the PWM control signal at the beginning of a next PWM cycle.