US Patent No. 9,356,117

METHOD FOR FORMING AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS


Patent No. 9,356,117
Issue Date May 31, 2016
Title Method For Forming Avalanche Energy Handling Capable Iii-nitride Transistors
Inventorship Sameer Pendharkar, Allen, TX (US)
Naveen Tipirneni, Plano, TX (US)
Assignee TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)

Claim of US Patent No. 9,356,117

1. A method of forming a semiconductor device, comprising the steps of:
forming a GaN FET by a process comprising the steps of:
providing a substrate;
forming an low-defect layer comprising gallium nitride over said substrate;
forming a barrier layer comprising AlxGa1?xN on said low-defect layer, so that a two-dimensional electron gas is generated in said low-defect layer just below said barrier
layer, said two-dimensional electron gas providing a conductive channel of said GaN FET;

forming a gate over said barrier layer; and
forming source and drain contacts to make tunneling connections to said two-dimensional electron gas;
forming an overvoltage clamping component, and electrically coupling a first end of said overvoltage clamping component to
a drain node of said GaN FET, said overvoltage clamping component being configured to conduct insignificant current when a
voltage at said drain node is less than a safe voltage limit which is less than a breakdown voltage of said GaN FET; said
overvoltage clamping component being further configured to conduct significant current when said voltage at said drain node
of said GaN FET rises above said safe voltage limit;

forming a voltage dropping component, electrically coupling a first end of said voltage dropping component to a second end
of said overvoltage clamping component, and electrically coupling a second end of said voltage dropping component to a terminal
for a bias potential which provides an off-state bias for said GaN FET, said voltage dropping component being configured to
provide a voltage drop which increases as current from said overvoltage clamping component increases; and

configuring said semiconductor device to turn on said GaN FET when said voltage drop across said voltage dropping component
reaches a threshold value.