US Patent No. 9,291,675

BOUNDARY CONTROL SCAN CELLS, DATA CELLS, RESYNCHRONIZATION MEMORIES, AND MULTIPLEXERS


Patent No. 9,291,675
Issue Date March 22, 2015
Title Boundary Control Scan Cells, Data Cells, Resynchronization Memories, And Multiplexers
Inventorship Lee D. Whetsel, Parker, TX (US)
Assignee TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US)

Claim of US Patent No. 9,291,675

1. An integrated circuit comprising:
A. a first circuit having data input leads connected to the inputs of input data buffers, control output leads connected to
the outputs of control output buffers, and a first scan path coupled between a test data input lead and a test data output
lead, the first scan path including:

i. a first control scan cell having a functional data input, a functional data output connected to an input of a first control
output buffer, a test data input coupled to the test data input lead, and a test data output separate from the functional
data output;

ii. first data scan cells, each first data scan cell having a functional data input connected to a data output of one data
input buffer, a test data input, a functional data output, and a test data output, the first data scan cells being connected
in a series, the test data input of the initial first data scan cell in the series being connected to the test data output
of the first control scan cell, and the test data input of each successive first data scan cell in the series being connected
to the test data output of the previous first data scan cell;

iii. a resynchronization memory having a test data input connected to the test data output of the first control scan cell
and a test data output;

iv. multiplexer circuitry having one input connected to the test data output of the last first data scan cell in the series,
another input connected to the test data output of the resynchronization memory, and an output; and

v. a second control scan cell having a functional data input, a functional data output connected to the input of a second
control output buffer, a test data input coupled to the output of the multiplexer, and a test data output separate from the
functional data output coupled to the test data output lead;

B. a second circuit having data output leads coupled to respective data input leads of the first circuit and having a control
input lead coupled to a control output lead of the first circuit, the data output leads being connected to the outputs of
tri-state data output buffers, each tri-state data output buffer having a tri-state control input for, when active, placing
the output of the tri-state data output buffer in a high impedance output state, the control input lead being connected to
the input of a control input buffer, and a second scan path coupled between the test data input lead and the test data output
lead, the second scan path including:

i. a third control scan cell having a functional data input connected to the output of the control input buffer, a functional
data output connected to the tri-state control inputs of all the data output tri-state buffers, a test data input coupled
to the test data input lead, and a test data output separate from the functional data output;

ii. second data scan cells, each second data scan cell having a functional data input, a test data input, a functional data
output, and a test data output, the second data scan cells being connected in series, the test data input of the initial second
data scan cell in the series being connected to the test data output of the third control scan cell, and the test data input
of each successive second data scan cell being connected to the test data output of the previous second data scan cell, the
functional data output of each second data scan cell being connected to the data input of one tri-state data output buffer;

iii. a resynchronization memory having a test data input connected to the test data output of the third control scan cell
and a test data output; and

iv. multiplexer circuitry having one input connected to the test data output of the last second data scan cell in the series,
another input connected to the test data output of the resynchronization memory, and an output coupled to the test data output
lead; and

C. leads coupling the first and second scan paths between the test data input lead and the test data output lead.