US Patent No. 9,258,015

DECODER WITH SELECTIVE ITERATION SCHEDULING


Patent No. 9,258,015
Issue Date February 09, 2016 
Title Decoder With Selective Iteration Scheduling
Inventorship Tomer Ish-Shalom, Raanana (IL)
Ronen Dar, Tel Aviv (IL)
Micha Anholt, Tel Aviv (IL)
Assignee Apple Inc., Cupertino, CA (US)

Claim of US Patent No. 9,258,015

1. A method, comprising:
decoding a code word of an Error Correction Code (ECC) by performing a sequence of iterations, such that each iteration involves
processing of multiple variable nodes, wherein the ECC is represented by a set of check equations;

for one or more selected variable node processors, evaluating a number of unsatisfied check equations that are defined over
one or more variables held respectively by the one or more selected variable node processors, and, omitting the one or more
selected variable node processors from a given iteration in the sequence in response to determining that the number of unsatisfied
check equations meets a predefined skipping criterion; and

clearing an indication that a particular variable node processor should be skipped in a current iteration in response to a
determining that the particular variable node processor was skipped in a previous iteration.