US Patent No. 9,257,410

PACKAGE ASSEMBLY INCLUDING A SEMICONDUCTOR SUBSTRATE IN WHICH A FIRST PORTION OF A SURFACE OF THE SEMICONDUCTOR SUBSTRATE IS RECESSED RELATIVE TO A SECOND PORTION OF THE SURFACE OF THE SEMICONDUCTOR SUBSTRATE TO FORM A RECESSED RE


Patent No. 9,257,410
Issue Date February 09, 2016 
Title Package Assembly Including A Semiconductor Substrate In Which A First Portion Of A Surface Of The Semiconductor Substrate Is Recessed Relative To A Second Portion Of The Surface Of The Semiconductor Substrate To Form A Recessed Re
Inventorship Albert Wu, Palo Alto, CA (US)
Roawen Chen, Monte Sereno, CA (US)
Chung Chyung Han, San Jose, CA (US)
Shiann-Ming Liou, Campbell, CA (US)
Chien-Chuan Wei, Los Gatos, CA (US)
Runzi Chang, San Jose, CA (US)
Scott Wu, San Jose, CA (US)
Chuan-Cheng Cheng, Fremont, CA (US)
Assignee Marvell World Trade Ltd., St. Michael (BB)

Claim of US Patent No. 9,257,410

1. An apparatus comprising:
a semiconductor substrate having
a first surface,
a second surface that is disposed opposite to the first surface, wherein (i) at least a first portion of the first surface
is recessed relative to a second portion of the first surface to form a first recessed region of the semiconductor substrate
and (ii) a second recessed region is formed from at least a portion of the second surface of the semiconductor substrate,
and

one or more vias formed in the first recessed region of the semiconductor substrate, the one or more vias to provide an electrical
or thermal pathway between the first surface and the second surface of the semiconductor substrate;

a first die coupled to the semiconductor substrate, the first die being electrically coupled to the one or more vias formed
in the first recessed region of the semiconductor substrate;

a first redistribution layer formed on the first surface of the semiconductor substrate, wherein (i) the first die is coupled
to the first surface of the semiconductor substrate via the first redistribution layer, and (ii) the first die is coupled
to the first redistribution layer via one or more first bumps;

a second redistribution layer formed on the second surface of the semiconductor substrate; and
a second die (i) coupled to the second surface of the semiconductor substrate via the second redistribution layer, and (ii)
coupled to the second redistribution layer via one or more second bumps.