1. A phase-locked loop (PLL) comprising:
a capacitor based digital to analog converter (DAC) coupled to receive a digital indication of quantization noise and to supply
a quantization noise correction voltage to adjust a phase error voltage to create a combined voltage with reduced quantization
noise, wherein the phase error voltage is indicative of a phase error corresponding to a time difference between a reference
signal and a feedback signal from an oscillator controlled at least in part based on a value of the combined voltage.