1. A method for implementing task-process-table based hardware control, comprising:
step A: dividing tasks that has to be performed by a hardware circuit into multiple sub-processes, and determining a depth
of the task process table according to a number of the sub-processes;
step B: determining a bit width of the task process table according to control information of the hardware circuit corresponding
to each of the sub-processes and a number of clock cycles occupied by hardware processing for the sub-process (SPAN), and
generating the task process table; and
step C: successively starting a hardware unit corresponding to each of the sub-processes to perform the sub-processes, in
an order of the sub-processes, under control of the control information in the task process table.