US Patent No. 9,225,347

OSCILLATOR


Patent No. 9,225,347
Issue Date December 29, 2015
Title Oscillator
Inventorship Kazuo Akaike, Saitama (JP)
Tsukasa Kobata, Saitama (JP)
Assignee NIHON DEMPA KOGYO CO., LTD., Tokyo (JP)

Claim of US Patent No. 9,225,347

1. An oscillator configured to receive a frequency setting value input to an oscillation circuit portion and obtain a frequency
output corresponding to the frequency setting value from the oscillation circuit portion, the oscillator comprising:
a normal frequency output portion that outputs a digital value corresponding to a normal frequency;
a frequency adjustment factor output portion that outputs a digital value corresponding to a frequency ratio to set a frequency
adjustment factor with respect to the normal frequency based on the frequency ratio;

an interpolation circuit portion that performs interpolation for a digital value of lower-order bits out of the digital value
output from the frequency adjustment factor output portion;

a first adder that adds an output value of the interpolation circuit portion and a digital value of higher-order bits out
of the digital value output from the frequency adjustment factor output portion to output an addition value for designating
the frequency setting value,

a gain output portion that outputs a digital value corresponding to a gain to be multiplied to the addition value output from
the first adder;

a multiplier that multiplies the gain output from the gain output portion by the addition value output from the first adder;
and

a second adder that adds the digital value output from the normal frequency output portion and a digital value output from
the multiplier and outputs an addition value as a frequency setting signal,

wherein a signal output from the interpolation circuit portion is sequential data having first and second values different
from each other and output in synchronization with a clock signal, and

output counts of the first and second values are determined based on a ratio corresponding to the digital value of the lower-order
bits,

wherein a lower limit of a variable frequency width represented as a frequency ratio is allocated to a minimum value of the
digital value that is capable of being set in the frequency adjustment factor output portion,

an upper limit of the variable frequency width represented as a frequency ratio is allocated to a maximum value of the digital
value that is capable of being set in the frequency adjustment factor output portion.