US Patent No. 9,105,319

MULTIPORT MEMORY ARCHITECTURE


Patent No. 9,105,319
Issue Date August 11, 2015
Title Multiport Memory Architecture
Inventorship Winston Lee, Palo Alto, CA (US)
Sehat Sutardja, Los Altos Hills, CA (US)
Donald Pannell, Cupertino, CA (US)
Assignee Marvell World Trade Ltd., St. Michael (BB)

Claim of US Patent No. 9,105,319

1. A method comprising:
receiving, at one of a plurality of port buffers, serial data directly from one of a plurality of data ports;
converting, via the port buffer and at a first frequency, the serial data received directly from the data port to n-bit-wide
words of parallel data;

buffering a k-word-long block of the n-bit-wide words of parallel data into a line of the port buffer as k*n bits of data
by sequentially writing k words of the n-bit-wide words of parallel data into k data storage elements of the line of the port
buffer; and

transmitting, from the port buffer and at a second frequency, the k*n bits of data directly to the multi-port memory array
via a first write bus of the multi-port memory array effective to write the k*n bits of data to the memory array, the multi-port
memory array having a second write bus through which the multi-port memory is configured to receive another k*n bits of data
from another of the plurality of port buffers, the first frequency of the converting being different from the second frequency
of the transmitting by at least 10 percent of the second frequency.