US Patent No. 9,083,525

METHOD AND APPARATUS FOR GENERATING JITTER TEST PATTERNS ON A HIGH PERFORMANCE SERIAL BUS


Patent No. 9,083,525
Issue Date July 14, 2015
Title Method And Apparatus For Generating Jitter Test Patterns On A High Performance Serial Bus
Inventorship Colin Whitby-Strevens, Ben Lomond, CA (US)
Assignee Apple Inc., Cupertino, CA (US)

Claim of US Patent No. 9,083,525

1. An apparatus configured to transmit a jitter test pattern over a communications bus to a device under test, the apparatus
comprising:
a port configured to at least transmit and receive data over the communications bus;
a transmission scrambler in data communication with the port; and
computerized logic in data communication with the port and the transmission scrambler, the logic configured to cause the apparatus
to:

generate one or more jitter test patterns comprising at least one asynchronous packet;
transmit the one or more jitter test patterns to the device under test;
disable the transmission scrambler after synchronization with the device under test has been achieved; and
retransmit the one or more jitter test patterns at least once to the device under test.