US Patent No. 11,116,080

WIRING SUBSTRATE


Patent No. 11,116,080
Issue Date September 07, 2021
Title Wiring Substrate
Inventorship Takenobu Nakamura, Ogaki (JP)
Takahiro Yamazaki, Ogaki (JP)
Takashi Yamauchi, Ogaki (JP)
Toshihide Makino, Ogaki (JP)
Assignee IBIDEN CO., LTD., Ogaki (JP)

Claim of US Patent No. 11,116,080


1. A wiring substrate, comprising:a core layer;
a plurality of first conductor layers formed on a first surface of the core layer and comprising a first inner conductor layer formed on the first surface of the core layer, a first outer conductor layer forming an outermost conductor layer on a first surface side of the core layer, and a first intermediate conductor layer formed between the first inner conductor layer and the first outer conductor layer;
a plurality of second conductor layers formed on a second surface of the core layer on an opposite side with respect to the first surface of the core layer and comprising a second inner conductor layer formed on the second surface of the core layer, a second outer conductor layer forming an outermost conductor layer on a second surface side of the core layer, and a second intermediate conductor layer formed between the second inner conductor layer and the second outer conductor layer;
a plurality of interlayer insulating layers interposed between the first inner conductor layer and the first intermediate conductor layer, between the second inner conductor layer and the second intermediate conductor layer, between the first intermediate conductor layer and the first outer conductor layer, and between the second intermediate conductor layer and the second outer conductor layer; and
a plurality of via conductors formed in the interlayer insulating layers such that each of the via conductors connects two conductor layers in one of the first and second conductor layers through one of the interlayer insulating layers and is integrally formed with one of the two conductor layers on a side away from the core layer,
wherein at least one of the first and second inner conductor layers comprises a first conductor layer structure including a metal foil layer and a plating film layer, at least one of the first and second outer conductor layers comprises the first conductor layer structure, at least one of the first and second intermediate conductor layers comprises a second conductor layer structure including a metal foil layer and a plating film layer, and the plurality of via conductors includes a first group of via conductors integrally formed with the first conductor layer structure in at least one of the first and second outer conductor layers such that the first group of via conductors includes a plurality of constricted via conductors each of which has a constricted portion between the two conductor layers being connected thereby, and a plurality of non-constricted via conductors each of which does not have the constricted portion.