1. A semiconductor memory device comprising:a memory cell array including a plurality of memory cells, each memory cell being capable of storing data;
a sense circuit configured to sense the data stored in a memory cell of the plurality of memory cells;
a first data latch configured to latch data sensed from the memory cell by the sense circuit;
a second data latch configured to receive the data from the first data latch;
a status register configured to store information indicating whether the semiconductor memory device is in a ready state or in a busy state;
an input/output circuit configured to output from the semiconductor memory device the data received from the second data latch and the information received from the status register; and
a control circuit configured to control the status register to store the information indicating the busy state upon receipt of a read command and to control the status register to store the information indicating the ready state, before completion of transfer of the data sensed from the memory cell from the first data latch to the second data latch.