1. A terminal comprising:a transmitter that transmits an uplink control signal in an uplink control channel; and
a processor that maps the uplink control channel according to given uplink control channel format 2 or 3 to two or more interlaces,
wherein the interlaces are each configured with a plurality of frequency resources which are discretely distributed in a frequency direction, and
the processor exerts control to apply an orthogonal code to the uplink control channel, mapped to the plurality of frequency resources which are discretely distributed in the frequency direction, in a frequency domain.