US Patent No. 10,990,721

DELAY DEPENDENCE IN PHYSICALLY AWARE CELL CLONING


Patent No. 10,990,721
Issue Date April 27, 2021
Title Delay Dependence In Physically Aware Cell Cloning
Inventorship William Robert Reece, Over (GB)
Thomas Andrew Newton, Great Cambourne (GB)
Zhuo Li, Austin, TX (US)
Assignee Cadence Design Systems, Inc., San Jose, CA (US)

Claim of US Patent No. 10,990,721

1. A computer-implemented method comprising:accessing, using one or more hardware processors, a circuit design stored in memory, the circuit design comprising a plurality of flip-flop elements having clock inputs provided by a routing tree;
identifying, using the one or more hardware processors, an associated delay for each flip-flop element of the plurality of flip-flop elements;
clustering, using the one or more hardware processors, individual flip-flop elements within the plurality of flip-flop elements based on the associated delays of the individual flip-flop elements to generate at least a first cluster of flip-flop elements and a second cluster of flip-flop elements, the clustering comprising:
identifying a minimum delay for an individual flip-flop element of the plurality of flip-flip elements;
defining a first delay window from the minimum delay to a window size:
defining a second delay window from a maximum delay of the first delay window to the window size;
generating the first cluster of flip-flop elements as a first set of flip-flop elements of the plurality of flip-flop elements having the associated delay within the first delay window; and
generating the second cluster of flip-flop elements as a second set of flip-flop elements of the plurality of flip-flop elements having the associated delay within the second delay window;
grouping, using the one or more hardware processors, single flip-flop elements within the first cluster based on physical characteristics of the single flip-flop elements to generate at least a first delay group of flip-flop elements within the first cluster and a second delay group of flip-flop elements within the first cluster;
generating, using the one or more hardware processors, an updated circuit design by updating the routing tree for the circuit design using the first delay group and the second delay group; and
generating, using the one or more hardware processors, a set of masks based on the updated circuit design, the set of masks being configured for use in generating an integrated circuit that comprises the updated circuit design.