US Patent No. 10,925,152
DIELECTRIC COATING FOR CROSSTALK REDUCTION
| Patent No. | 10,925,152 |
|---|---|
| Issue Date | February 16, 2021 |
| Title | Dielectric Coating For Crosstalk Reduction |
| Inventorship | Albert Sutono, Chandler, AZ (US) Xiaoning Ye, Portland, OR (US) Jimmy Hsu, Taoyuan (TW) Daniel Hull, Chandler, AZ (US) |
| Assignee | Intel Corporation, Santa Clara, CA (US) |
Claim of US Patent No. 10,925,152
1. A printed circuit board (PCB), comprising:a substrate;
first and second microstrip conductors located on a surface of the substrate;
a solder mask covering the surface of the substrate and the first and second microstrip conductors; and
a dielectric coating disposed on the solder mask, on an opposite side of the solder mask from the first and second microstrip conductors, wherein a thickness of the dielectric coating is selected to provide a ratio of capacitive coupling to self capacitance for each of the first and second microstrip conductors to be approximately equal, within 25%, to a ratio of inductive coupling to self inductance for each of the first and second microstrip conductors.
first and second microstrip conductors located on a surface of the substrate;
a solder mask covering the surface of the substrate and the first and second microstrip conductors; and
a dielectric coating disposed on the solder mask, on an opposite side of the solder mask from the first and second microstrip conductors, wherein a thickness of the dielectric coating is selected to provide a ratio of capacitive coupling to self capacitance for each of the first and second microstrip conductors to be approximately equal, within 25%, to a ratio of inductive coupling to self inductance for each of the first and second microstrip conductors.