US Patent No. 10,893,616

MULTILAYER PRINTED WIRING BOARD PRODUCTION METHOD, ADHESIVE LAYER-EQUIPPED METAL FOIL, METAL-CLAD LAMINATE, AND MULTILAYER PRINTED WIRING BOARD


Patent No. 10,893,616
Issue Date January 12, 2021
Title Multilayer Printed Wiring Board Production Method, Adhesive Layer-equipped Metal Foil, Metal-clad Laminate, And Multilayer Printed Wiring Board
Inventorship Hitoshi Onozeki, Tokyo (JP)
Tsubasa Inoue, Tokyo (JP)
Katsuji Yamagishi, Tokyo (JP)
Hiroshi Shimizu, Tokyo (JP)
Assignee Showa Denko Materials Co., Ltd., Tokyo (JP)

Claim of US Patent No. 10,893,616

1. A method of producing a multi-layered printed wiring board, comprising the following steps 1 to 3:Step 1: a step of laminating a multilayer structure comprising, in order, a support, a metal foil and an organic adhesive layer, on a substrate with an inner layer circuit via an organic insulating resin layer, with the organic insulating resin layer being provided between the organic adhesive layer and the substrate with an inner layer circuit, the inner layer circuit having a thickness of 10 to 30 ?m, the metal foil having a thickness of 3 ?m or less and 1/10 to ? relative to the thickness of the inner layer circuit, and the organic adhesive layer having a thickness of 1 to 10 ?m, and then releasing the support to form a laminated sheet (a) having the metal foil as an outer layer metal foil layer;
Step 2: a step of irradiating the laminated sheet (a) with a laser to bore the outer layer metal foil layer, the organic adhesive layer, and the organic insulating resin layer to form a bored laminated sheet (b) having a blind via hole; and
Step 3: a step of forming an outer layer circuit connected with the inner layer circuit through the following steps 3-1 to 3-4;
Step 3-1: a step of removing the outer layer metal foil layer of the bored laminated sheet (b) formed in the step 2 by etching and then forming an outer layer copper layer having a thickness of 0.1 to 2 ?m on the bored laminated sheet (b);
Step 3-2: a step of forming a resist pattern by a resist applied on the outer layer copper layer;
Step 3-3: a step of forming a circuit layer on the surface of the outer layer copper layer on which the resist pattern is not formed, by electrolytic copper plating; and
Step 3-4: a step of removing the resist pattern and then removing the exposed outer layer copper layer by etching, thereby forming an outer layer circuit connected with the inner layer circuit.