US Patent No. 10,798,822

METHOD OF MANUFACTURING A COMPONENT EMBEDDED PACKAGE CARRIER


Patent No. 10,798,822
Issue Date October 06, 2020
Title Method Of Manufacturing A Component Embedded Package Carrier
Inventorship Jing-Cyuan Yang, Hsinchu County (TW)
Assignee Subtron Technology Co., Ltd., Hsinchu County (TW)

Claim of US Patent No. 10,798,822

1. A manufacturing method of a component embedded package carrier, comprising:forming a core layer, the core layer comprising a dielectric layer, an opening of the core layer, a first patterned conductive layer, a second patterned conductive layer and a plurality of conductive through hole structures, the dielectric layer having an upper surface and a lower surface opposite each other, the opening passing through the dielectric layer, the first patterned conductive layer being located on the upper surface, the second patterned conductive layer being located on the lower surface, and the conductive through hole structures passing through the dielectric layer and connecting the first patterned conductive layer with the second patterned conductive layer, wherein forming the core layer comprises:
providing the dielectric layer, a first copper foil layer and a second copper foil layer, the first copper foil layer being disposed on the upper surface of the dielectric layer, and the second copper foil layer being disposed on the lower surface of the dielectric layer;
forming a plurality of through holes, the through holes passing through the dielectric layer, the first copper foil layer and the second copper foil layer;
forming a first conductive material layer on the first copper foil layer and the second copper foil layer, wherein the first conductive material layer fills the through holes and entirely covers the first copper foil layer and the second copper foil layer;
patterning the first conductive material layer, the first copper foil layer and the second copper foil layer, thereby defining the conductive through hole structures, the first patterned conductive layer and the second patterned conductive layer; and
forming the opening of the core layer, after patterning the first conductive material layer, the first copper foil layer and the second copper foil layer;
disposing at least one electronic component inside the opening of the core layer;
laminating a first insulating layer and a first circuit layer located on the first insulating layer onto the first patterned conductive layer, wherein the first insulating layer covers the first patterned conductive layer and the upper surface of the dielectric layer and is filled into the opening of the core layer;
laminating a second insulating layer and a second circuit layer located on the second insulating layer onto the second patterned conductive layer, wherein the second insulating layer covers the second patterned conductive layer and the lower surface of the dielectric layer and is filled into the opening of the core layer, and the first insulating layer and the second insulating layer completely fill the opening of the core layer and completely encapsulate the electronic component;
forming a plurality of conductive blind via structures, a third patterned conductive layer and a fourth patterned conductive layer, the third patterned conductive layer being located on the first insulating layer and comprising the first circuit layer, the fourth patterned conductive layer being located on the second insulating layer and comprising the second circuit layer, and the conductive blind via structures connecting the third patterned conductive layer with the conductive through hole structures, the fourth patterned conductive layer with the conductive through hole structures, the third patterned conductive layer with the electronic component and the fourth patterned conductive layer with the electronic component, wherein forming the conductive blind via structures, the third patterned conductive layer and the fourth patterned conductive layer comprises:
forming a plurality of blind vias, the blind vias extending from the first circuit layer to the first patterned conductive layer and the electronic component and extending from the second circuit layer to the second patterned conductive layer and the electronic component;
forming a second conductive material layer on the first circuit layer and the second circuit layer, wherein the second conductive material layer fills the blind vias and entirely covers the first circuit layer and the second circuit layer; and
patterning the second conductive material layer, the first circuit layer and the second circuit layer, thereby defining the conductive blind via structures, the third patterned conductive layer and the fourth patterned conductive layer; and
forming a first protecting layer and a second protecting layer, the first protecting layer having a first roughness surface and covering the third patterned conductive layer and a portion of the first insulating layer, and the second protecting layer having a second roughness surface and covering the fourth patterned conductive layer and a portion of the second insulating layer.