US Patent No. 10,694,651

CHIP-PLACING METHOD PERFORMING AN IMAGE ALIGNMENT FOR CHIP PLACEMENT AND CHIP-PLACING APPARATUS THEREOF


Patent No. 10,694,651
Issue Date June 23, 2020
Title Chip-placing Method Performing An Image Alignment For Chip Placement And Chip-placing Apparatus Thereof
Inventorship Yen-Hao Lu, Hsinchu (TW)
Assignee SAUL TECH TECHNOLOGY CO., LTD., Hsinchu (TW)

Claim of US Patent No. 10,694,651

1. A chip-placing method that performs an image alignment for chip placement, the chip-placing method being applied while a chip-placing member of a chip-placement apparatus is configured to move to a to-be-placed location on a substrate, the chip-placing apparatus including a chip-placing device, a reference-image capturing device and an alignment-image capture device, the chip-placing device including the chip-placing member and a marking member adjacent to the chip-placing member, the chip-placing method comprising:a chip pick-up step that enables the chip-placing member to suck a chip;
a reference-image capturing step that enables the reference-image capturing device to capture an image of the marking member from an opposite direction of the chip-placing device, and captures an image of the chip sucked by the chip-placing member so as to obtain a relative position information of the chip in relation to the marking member;
an alignment-image capturing step that enables the alignment-image capture device to capture, from a backside of the chip-placing device, an image showing the marking member and the substrate so as to obtain a relative position information of the marking member in relation to the substrate;
a calculating and processing step that obtains a position calibration relationship information of the position of the chip sucked by the chip-placing member in relation to a to-be-placed location of the substrate according to the relative position information of the chip in relation to the marking member and the relative position information of the marking member in relation to the substrate;
a calibration adjusting step that calibrates a relative position of the chip-placing member in relation to the to-be-placed location according to the position calibration relationship information so as to align the position of the chip sucked by the chip-placing member with the to-be-placed location; and
a chip placing step that enables the chip-placing member to place the chip,
wherein the reference-image capturing step includes a two-separate capturing sub-step and an image-overlapping sub-step, the two-separate capturing sub-step enabling the reference-image capturing device in a reference position to respectively capture the image of the marking member and the image of the chip sucked by the chip-placing member, and the image-overlapping sub-step enables the image of the marking member and the image of the chip sucked by the chip-placing member to be overlapped so as to obtain the relative position information of the chip in relation to the marking member,
wherein the chip-placing member and the marking member are disposed as separated with each other with a predetermined fixed distance such that the two-separate capturing sub-step enables the chip-placing device to move the predetermined fixed distance to enable the reference-image capturing device in the reference position to respectively capture the image of the marking member and the image of the chip sucked by the chip-placing member.