US Patent No. 10,599,579

DYNAMIC CACHE PARTITIONING IN A PERSISTENT MEMORY MODULE


Patent No. 10,599,579
Issue Date March 24, 2020
Title Dynamic Cache Partitioning In A Persistent Memory Module
Inventorship Karthik Kumar, Chandler, AZ (US)
Francesc Guim Bernat, Barcelona (ES)
Benjamin Graniello, Chandler, AZ (US)
Thomas Willhalm, Sandhausen (DE)
Mustafa Hajeer, Hillsboro, OR (US)
Assignee Intel Corporation, Santa Clara, CA (US)

Claim of US Patent No. 10,599,579

1. A memory module comprising:a persistent memory to store data;
a cache; and
control logic coupled to the persistent memory and the cache, the control logic to monitor write and read accesses to/from the persistent memory and to dynamically partition the cache to assign a first portion of the cache for read cache and a second portion of the cache for write cache based on monitored read and write accesses to prioritize read and write operations to the persistent memory, the control logic to monitor a hit rate in the first portion of the cache and to reduce a size of the first portion of the cache and to increase a size of the second portion of the cache if the hit rate is below a minimum threshold.