US Patent No. 10,599,571

INSTRUCTION PREFETCH MECHANISM


Patent No. 10,599,571
Issue Date March 24, 2020
Title Instruction Prefetch Mechanism
Inventorship Vasileios Porpodas, San Jose, CA (US)
Guei-Yuan Lueh, San Jose, CA (US)
Subramaniam Maiyuran, Gold River, CA (US)
Wei-Yu Chen, San Jose, CA (US)
Assignee Intel Corporation, Santa Clara, CA (US)

Claim of US Patent No. 10,599,571

1. An apparatus to facilitate data prefetching comprising:one or more processors to track information for memory instructions in first program code executed at one or more execution units (EUs) that trigger a cache miss, provide the tracked information for generation of second program code, upload the second program code to an instruction memory during execution of the first program code and execute the second program code at the one or more EUs in place of the first program code, wherein the second program code includes one or more pre-fetch instructions inserted into one or more place-holder addresses in the instruction memory to prefetch data for execution of one or more of the memory instructions that triggered a cache miss in place of the first program code.