US Patent No. 10,599,504

DYNAMIC ADJUSTMENT OF REFRESH RATE


Patent No. 10,599,504
Issue Date March 24, 2020
Title Dynamic Adjustment Of Refresh Rate
Inventorship Christopher James BeSerra, Federal Way, WA (US)
Gary S. Shankman, Olympia, WA (US)
Gavin Akira Ebisuzaki, Bellevue, WA (US)
Terry Lee Nissley, Lacey, WA (US)
Assignee Amazon Technologies, Inc., Seattle, WA (US)

Claim of US Patent No. 10,599,504

1. A method comprising:receiving an indication that a correctable error is detected when reading from dynamic random access memory (DRAM) in communication with a processor, the processor being in a fleet of processors;
using a baseboard management controller in communication with the processor to calculate an error rate of reading from the DRAM and to determine that the error rate exceeds a pre-determined threshold error rate, the baseboard management controller in communication with a health monitoring service configured to monitor the operational status for the fleet of processors;
determining that a refresh rate of the DRAM exceeds a default refresh rate of the DRAM;
without rebooting the processor, using the baseboard management controller to initiate programming of a memory controller to increase both the refresh rate and a patrol scrub rate of the DRAM in response to determining that the error rate exceeds the pre-determined threshold error rate and that the refresh rate of the DRAM exceeds the default refresh rate of the DRAM, wherein the patrol scrub rate is different from the refresh rate;
in response to increasing both the refresh rate and the patrol scrub rate of the DRAM, using the baseboard management controller to transmit a status message, indicating the increase of the refresh rate and the patrol scrub rate, to the health monitoring service that is configured to monitor the operational status for the fleet of processors, the health monitoring service executing on a management server computer; and
using the health monitoring service to determine that a denial of service attack is underway on the fleet of processors based on the refresh rate and the patrol scrub rate of the DRAM being increased.