US Patent No. 10,580,505

ERASING METHOD USED IN FLASH MEMORY


Patent No. 10,580,505
Issue Date March 03, 2020
Title Erasing Method Used In Flash Memory
Inventorship Chih-Hao Chen, New Taipei (TW)
Assignee ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC., (TW)

Claim of US Patent No. 10,580,505

1. An erasing method used in a flash memory comprising at least one memory block divided into a plurality of memory sectors, comprising:performing an erasing and verifying process on the memory block, and setting an erasing flag to be logically true if the memory block is erased;
performing an over-erased correcting and verifying process on the memory block if the erasing flag is logically true, setting an over-erased correction flag to be logically true and a memory sector enable signal to be asserted if an over-erased correction is performed on the memory block, and then resetting both of the erasing flag and the over-erased correction flag to be logically false;
when the memory sector enable signal is asserted, performing the erasing and verifying process sequentially on the memory sectors of the memory block, and setting the erasing flag to be logically true if at least one of the memory sectors is erased; and
when the memory sector enable signal is asserted and the erasing flag is logically true, performing the over-erased correcting and verifying process sequentially on the memory sectors of the memory block, setting the over-erased correction flag to be logically true if the over-erased correction is performed on at least one of the memory sectors, and then resetting both of the erasing flag and the over-erased correction flag to be logically false.