1. A process of utilizing a pin array that includes multiple segmented pins for forming selectively plated through holes, the process comprising:forming a printed circuit board (PCB) laminate structure that includes a plurality of spinel-doped core layers and a plurality of through holes, wherein each spinel-doped core layer of the plurality of spinel-doped core layers includes a heat-activated spinel material incorporated into a dielectric material;
aligning individual segmented pins of a plurality of segmented pins of a pin array with corresponding through holes of the plurality of through holes of the PCB laminate structure, wherein each segmented pin of the plurality of segmented pins includes one or more heated segments and one or more insulating segments;
inserting the plurality of segmented pins of the pin array into the corresponding through holes;
generating heat within each heated segment of the plurality of segmented pins that is sufficient to form metal nuclei sites in selected regions of the plurality of spinel-doped core layers that are adjacent to portions of the individual through holes that contain the one or more heated segments of the individual segmented pins, wherein the metal nuclei sites function as seed layers to enable formation of selectively plated through holes.