1. A memory device including a memory core, the memory device comprising:a parallel receiver circuit to receive commands comprising a plurality of bits synchronously with respect to a clock signal, the commands including a read command that specifies an access of data from the memory core;
a serial receiver circuit to receive serial data;
a serial driver circuit to transmit the serial data and to transmit status information pertaining to the access of data;
a plurality of output drivers to output the data, in parallel, after a delay time transpires from when the read command is received at the receiver circuit; and,
a resume signal driver to output a first indicator that the memory device is ready to not receive the clock signal, and a second indicator that the memory device is ready to receive the clock signal, the second indicator to be output before the data is ready to be output by the plurality of output drivers.