US Patent No. 10,558,584


Patent No. 10,558,584
Issue Date February 11, 2020
Title Employing Intermediary Structures For Facilitating Access To Secure Memory
Inventorship Krystof Zmudzinski, Forest Grove, OR (US)
Assignee Intel Corporation, Santa Clara, CA (US)

Claim of US Patent No. 10,558,584

1. A device configured to employ intermediary structures for facilitating access to secure memory, comprising:memory including an application, an operating system, firmware, and secure resources, wherein the firmware causes a secure driver to be loaded into the memory, wherein the secure driver is configured to:
facilitate communication between the application and the secure resources;
cause at least one section of the secure resources to be reserved as a secure page cache including at least one secure page slot; and
generate a linear address manager mapping that maps at least one pseudo page address in a linear address manager to the at least one secure page slot, wherein the linear address manager is included in the secure resources,
wherein to facilitate communication between the application and the secure resources includes to convert a virtual exception to a page fault that is passed to an operating system (OS) kernel, to the application, and to the secure driver.