US Patent No. 10,558,569


Patent No. 10,558,569
Issue Date February 11, 2020
Title Cache Controller For Non-volatile Memory
Inventorship Hans Boehm, Palo Alto, CA (US)
Dhruva Chakrabarti, Palo Alto, CA (US)
Assignee Hewlett Packard Enterprise Development LP, Houston, TX (US)

Claim of US Patent No. 10,558,569

1. A method comprising:monitoring, using a data structure storing address tags of dirty cache lines, a quantity of the dirty cache lines in a cache that includes cache lines storing data and respective address tags, the dirty cache lines corresponding to data in a main memory;
computing, by a cache controller or a processor, a threshold that is based on a capacity of the data structure and that is less than a cache line storage capacity of the cache wherein computing the threshold comprises adjusting the threshold by the cache controller or the processor based on a frequency of cache flushes from the cache to the main memory;
comparing the quantity of the dirty cache lines to the threshold; and
causing a write back by the cache controller of at least one of the dirty cache lines to the main memory in response to a store event that causes the quantity of the dirty cache lines to satisfy the threshold.