US Patent No. 10,510,402

MITIGATING WRITE DISTURBANCE IN DUAL PORT 8T SRAM


Patent No. 10,510,402
Issue Date December 17, 2019
Title Mitigating Write Disturbance In Dual Port 8t Sram
Inventorship M. Sultan M. Siddiqui, Noida (IN)
Sumit Srivastav, Benares (IN)
Dattatray Ramrao Wanjul, Nashik (IN)
Manankumar Suthar, Ahmedabad (IN)
Sudhir Kumar, Shastri Nagar (IN)
Assignee Synopsys, Inc., Mountain View, CA (US)

Claim of US Patent No. 10,510,402

1. A static random access memory (SRAM) device, the SRAM device comprising a plurality of dual-port SRAM cells arranged in rows and columns, each SRAM cell comprising:a pair of cross-coupled inverters having a first data port coupled to a first word line, a first bit line, and a first bit-complement line, and further having a second data port coupled to a second word line, a second bit line, and a second bit-complement line,
wherein the first bit line is connected to a first data terminal through a first data transmission switch responsive to a first port write signal, and to a second data terminal through, in series, a second data transmission switch responsive to a second port write signal and a first cross-connect switch responsive to a write disturb enable signal,
wherein the second bit line is connected to the second data terminal through a third data transmission switch responsive to the second port write signal, and to the first data terminal through, in series, a fourth data transmission switch responsive to the first port write signal and a second cross-connect switch responsive to the write disturb enable signal,
wherein the first bit-complement line is connected to a first data-complement terminal through a fifth data transmission switch responsive to the first port write signal, and to a second data-complement terminal through, in series, a sixth data transmission switch responsive to the second port write signal and a third cross-connect switch responsive to the write disturb enable signal, and
wherein the second bit-complement line is connected to the second data-complement terminal through a seventh data transmission switch responsive to the second port write signal, and to the first data-complement terminal through, in series, an eighth data transmission switch responsive to the first port write signal and a fourth cross-connect switch responsive to the write disturb enable signal.