1. A clock skew calibration apparatus comprising:an array of N time-interleaved analog-to-digital converters (TIADCs) receiving an analog input signal and configured to generate a stream of originating samples in a digital format, wherein the stream rate of the generated stream is one sample per period of an overall sampling clock (sclk) having a sampling frequency fS, and wherein the TIADCs are configured to receive an array of sampling clocks each having an individual sampling frequency of substantially fS/N; and,
a time skew extractor circuit comprising:
a summer circuit operatively coupled to receive the generated sample stream and a stream of delayed samples of the generated sample stream, wherein the summer circuit is configured to sum two consecutive samples from the generated sample stream; and,
a first absolute value circuit operatively coupled to the summer circuit, wherein the first absolute value circuit is operatively coupled to produce an array of clock error signals as a function of the summed consecutive samples of the generated sample stream.