1. A sample-and-hold circuit, comprising:a sampling capacitor;
an amplifier transistor; and
a noise reduction circuit including an integration capacitor and a feedback capacitor, the noise reduction circuit being configured to reduce noise via a four-phase operation including:
an auto-zero phase in which the feedback capacitor is discharged,
a feedback phase in which a gate voltage of the amplifier transistor is partially compensated through the feedback capacitor,
an integration phase in which the integration capacitor is charged, and
a feedforward phase in which the gate voltage of the amplifier transistor is fully compensated by a voltage on the integration capacitor through the feedback capacitor.