US Patent No. 10,433,432

PRINTED CIRCUIT BOARD AND CORRESPONDING METHOD FOR PRODUCING A PRINTED CIRCUIT BOARD


Patent No. 10,433,432
Issue Date October 01, 2019
Title Printed Circuit Board And Corresponding Method For Producing A Printed Circuit Board
Inventorship Uwe Hassel, Hockenheim (DE)
Assignee

Claim of US Patent No. 10,433,432

1. A method for producing a printed circuit board, the printed circuit board having at least one substrate layer, a metallic base layer on an upper surface and a lower surface of the at least one substrate layer, and a signal line on the upper surface and on the lower surface of the at least one substrate layer, the method comprising:boring at least one via hole through the printed circuit board having the at least one substrate layer and the metallic base layer;
depositing a first sublayer of a conductive layer on an upper surface of the metallic base layer on the upper surface of the at least one substrate layer and on a lower surface of the metallic base layer on the lower surface of the at least one substrate layer and a sleeve-sized conductive layer on a circumference of each of the at least one via hole between the upper surface and the lower surface of the metallic base layer;
removing the first sublayer of the conductive layer on the upper surface and the lower surface of the metallic base layer in all ranges which are positioned at least a specific minimum distance from each of the at least one via hole, wherein all ranges of the first sublayer of the conductive layer deposited on the upper surface and the lower surface of the metallic base layer that are located outside of a specific minimum distance from each of the at least one via hole are freed from the upper surface and the lower surface of the metallic base layer; and
removing the metallic base layer in ranges of the upper surface and the lower surface of the metallic base layer where the first sublayer of the conductive layer was removed from the upper surface and the lower surface of the metallic base layer to form signal lines or additional contact pads on the upper surface and the lower surface of the at least one substrate layer.