US Patent No. 10,433,429

METHOD OF ENHANCING FATIGUE LIFE OF GRID ARRAYS


Patent No. 10,433,429
Issue Date October 01, 2019
Title Method Of Enhancing Fatigue Life Of Grid Arrays
Inventorship James H. Kelly, West Newbury, MA (US)
Dmitry Tolpin, Sharon, MA (US)
Roger M. Maurais, Goffstown, NH (US)
Assignee Massachusetts Institute of Technology, Cambridge, MA (US)

Claim of US Patent No. 10,433,429

1. A method of assembling an electronic component onto a printed circuit board comprising:providing the printed circuit board having a printed circuit board coefficient of thermal expansion;
placing an array of pads on the printed circuit board;
applying connective material to the array of pads;
providing the electronic component, having an array of conducting posts and a different coefficient of thermal expansion than the printed circuit board coefficient of thermal expansion;
placing the electronic component on the printed circuit board so that the array of conducting posts of the electronic component is misaligned with the array of pads;
mounting the electronic component to the printed circuit board by heating the connective material and positioning the array of conducting posts against the connective material on the array of pads with ends of conducting posts of the array of conducting posts being drawn into closer alignment with pads of the array of pads wherein the conducting posts of the array of conducting posts have an angular tilt outwardly away from a center of the electronic component to the printed circuit board; and
maintaining the angular tilt outward of the array of conducting posts outwardly away from a center of the electronic component to the printed circuit board to a sufficient degree due to sufficient misalignment of the conducting posts with the array pads of the printed circuit board at 20 degrees Celsius and over a temperature range of 0 degrees Celsius to 100 degrees Celsius.