US Patent No. 10,433,421


Patent No. 10,433,421
Issue Date October 01, 2019
Title Reduced Capacitance Land Pad
Inventorship Zhichao Zhang, Chandler, AZ (US)
Tao Wu, Chandler, AZ (US)
Gaurav Chawla, Chandler, AZ (US)
Jeffrey Lee, Chandler, AZ (US)
Assignee Intel Corporation, Santa Clara, CA (US)

Claim of US Patent No. 10,433,421

1. A structure, comprising:a substrate having one or more dielectric layers including a conductive trace and a ground plane; and
a plurality of land pads on the surface of the substrate, the land pads each comprising:
a conductive portion electrically coupled with the conductive trace by one or more vias, the conductive portion having a contact area and a thickness, the contact area for making electrical contact to an individual land grid array (LGA) contact, wherein the contact area is parallel to the ground plane; and
one or more non-conductive voids in the contact area and extending through the thickness of the conductive portion, wherein the conductive portion is continuous around the one or more non-conductive voids.