US Patent No. 10,366,967


Patent No. 10,366,967
Issue Date July 30, 2019
Title Apparatus And Method For Multi-die Interconnection
Inventorship Jean-Philippe Fricker, Los Altos, CA (US)
Philip Ferolito, Los Altos, CA (US)
Assignee Cerebras Systems Inc., Los Altos, CA (US)

Claim of US Patent No. 10,366,967

1. A semiconductor having multiple, interconnected die, the semiconductor comprising:a substrate comprising a semiconductor wafer;
a plurality of die formed with the substrate;
a circuit layer formed at each of the plurality of die;
a plurality of inter-die connections that communicatively connect disparate die formed with the substrate, wherein each of the plurality of inter-die connections extends between each pair of adjacent die of the plurality of die, and wherein each of the plurality of die comprises a protective barrier comprising a seal ring that encompasses a periphery of each of the plurality of die,
wherein the plurality of die includes:
(i) a first subset of interior die defining an interior of the substrate, wherein the first subset of interior die has inter-die connections with adjacent die along all sides of the first subset of die;
(ii) a second subset of peripheral die defining a periphery of the substrate, wherein at least one side of each of the second subset of exterior die are formed without inter-die connections.