US Patent No. 10,366,330

FORMAL VERIFICATION RESULT PREDICTION


Patent No. 10,366,330
Issue Date July 30, 2019
Title Formal Verification Result Prediction
Inventorship Jinqing Yu, Fremont, CA (US)
Assignee SYNOPSYS, INC., Mountain View, CA (US)

Claim of US Patent No. 10,366,330

1. A computer-implemented method for verification analysis comprising:analyzing a design description for a semiconductor device to identify feature data for the semiconductor device using a directed-acyclic graph (DAG) representation for the design description and unrolling the DAG representation to coordinate sequential elements within the DAG representation, wherein the unrolling evaluates the sequential elements across a plurality of cycles;
accessing a plurality of verification engines to verify the semiconductor device;
orchestrating the plurality of verification engines, based on the feature data wherein the orchestrating selects one of a falsification engine and a prove engine to be utilized first in a verification process for the semiconductor device, wherein the prove engine is adapted to ensure that an improper state is not reached and wherein the falsification engine is adapted to trace an initial state to a bad state, and wherein the orchestrating includes selecting and scheduling other verification engines to be utilized in the verification process for the semiconductor device, and wherein the scheduling includes an order for executing the verification engines; and
predicting a verification result of the semiconductor device design.