1. An integrated circuit comprising a plurality of identical multiprocessor systems, wherein each multiprocessor system comprises:a first processor;
a second processor;
an interface means that is coupled to the first processor via a first bus, and that is coupled to the second processor via a second bus, wherein neither the first bus nor the second bus is a posted transaction bus, wherein the interface means includes a first register that is readable by the first processor via the first bus and a second register by the second processor via the second bus, wherein the interface means is for receiving information from one of the first and second buses in a write operation and for using that information to generate an atomic request, wherein the atomic request has a command portion, an address portion, and a data value portion; and
an atomic engine means for performing an atomic meter operation, wherein the atomic engine means receives the atomic request from the interface means, wherein the atomic engine means comprises:
a memory that stores pairs of credit values; and
a pipeline that uses the address portion of the atomic request to read a first credit value and a second credit value from the memory and then uses the first and second credit values along with the data value portion as input values to perform the atomic meter operation, wherein the pipeline outputs a result color value as a result of the atomic meter operation such that the result color value is then stored into one of the first and second registers in the interface means.