US Patent No. 10,352,991

EDGELESS LARGE AREA ASIC


Patent No. 10,352,991
Issue Date July 16, 2019
Title Edgeless Large Area Asic
Inventorship Farah Fahim, Glen Ellyn, IL (US)
Grzegorz W. Deptuch, Forest Park, IL (US)
Assignee Fermi Research Alliance, LLC, Batavia, IL (US)

Claim of US Patent No. 10,352,991

1. A three-dimensional integrated edgeless pixel detector apparatus, comprising:a large area multi-tier three-dimensional integrated edgeless detector having:
a sensor layer comprising a matrix of sensor pixels; and
at least two ASIC (Application Specific Integrated Circuit) layers comprising at least one analog tier and at least one digital tier configured for radiation spectroscopy or imaging with a zero suppressed readout or a full frame readout, wherein said at least one digital tier is edgeless and subdivided into a matrix of at least a 1×1 dimension of functionally complete and independent sub-chips, wherein each sub-chip among said sub-chips includes circuit elements that are not assigned to an individual pixel, but which is used to perform a reading out of a said sub-chip-related group of pixels without extending a placement of any portion of common circuitry external to an area occupied by said sub-chip-related group of pixels clamped in a readout manner with respect to a sub-chip among said sub-chips.