US Patent No. 10,338,821


Patent No. 10,338,821
Issue Date July 02, 2019
Title Memory Controller For High Latency Memory Devices
Inventorship Rajesh Ananthanarayanan, Mountain View, CA (US)
Jinying Shen, San Ramon, CA (US)
Amir Alavi, Irvine, CA (US)
Assignee SMART Modular Technologies, Inc., Newark, CA (US)

Claim of US Patent No. 10,338,821

1. A system comprising:a memory device; and
a register device configured to receive a host command and a host address, generate a module command and a physical address for a read transaction upon receiving the host command and the host address, send the module command and the physical address to the memory device, send dummy data to a host memory controller while the memory device retrieves actual data at the physical address, and send the actual data to the host memory controller when the actual data is available from the memory device.